QUBECS Development of Scalable Highly Integrated Quantum Bit Error Correction System

Objective

Overview

R&D Subjects

	Moonshot Goal 6 "Development of Scalable Highly Integrated Quantum Bit Error Correction System" Moonshot Goal 6 QUBECS: Quantum Bit Error Correction System
	* Moonshot International Symposium for Goal 6 held at April 23, 2021 (Public video site) * Introduction movie of our project on APS TV March meeting 2024 * *Nature*： Nature Focal Point on Quantum computing in Japan （Top page of the feature) 　　　　　"Quantum computers shoot for the moon" （Our project: QUBECS）


Project Manager: Kazutoshi Kobayashi
	Professor, Director,	Dept. of Electronics, Graduate School of Science and Technology, Kyoto Institute of Technology Kyoto Lab for a Greener Future, Kyoto Institute of Technology

Objective

R&D Subjects

R&D Subject 1

Backend for error correction

Overview: Overview: Research and develop a backend system for error correction which is scalable to the number of Qubits
Research Target: Prototype and demonstrate a backend system for qubit error correction which performs error syndrome analysis on a scale of 100s of physical qubits ay an acceptable thrroughput and latency. Show scalability for more physical qubits.

Research and development theme 1: Scalable backend system for error correction
	Principal Investigator: Kentaro Sano (RIKEN) Overview: Develop hardware algorithms for syndrome analysis, construct an FPGA cluster and demonstarte scalabe error correction with a prototype system of the FPGAs.
Development Goal: Develop a hardware algorithm that can analyze error syndromes obtained from the frontend with high throughput and low latency, and estimate the upper limit of performance achievement. In addition, we built an FPGA cluster interconnecting FPGA devices with a dedicated network and implemented a prototype backend system that can scale error correction processing up to 100s of physical qubits, and obtained the prospect of 1 million Qubit error correction expected in the future.

Research and development theme 2: ASIC implementation of QEC cores
	Principal Investigator: Junichiro Kadomoto (The University of Tokyo) Overview: Based on the knowledge of the FPGA cluster implementation in research theme 1, we consider the overall architecture of the backend hardware and develop a more scalable system through optimization by leveraging ASICs. We also study the implementation and execution schemes of error correction algorithms that are suitable for the ASIC-based system.
Development Goal: Optimal design of backend hardware for scalability, quantitative performance evaluation of quantum algorithms on the ASIC-based system.

Research and development theme 3: Dependable error correction backend
	Project promoter: Yasunori Osana (Kumamoto University) Overview: Achieve highly-reliable FPGA cluster and its interconnect for error correction backend.
Development Goal: Develop low-latency and highly reliable interconnects for FPGAs in both backend and frontend systems. Ethernet-based interconnect with high scalability and a dedicated protocol-based one for minimum latency is under development. Both of them are designed to be packet-loss-free and targeted to 100+ Gbps. Also, we'll investigate the reliability issues of the backend FPGA cluster itself, such as soft errors. Finding the solutions to these issues is crucial for system scaling after 2025.

Research and development theme 1: Advanced Qubit Control Frontend
		Principal Investigator: Takefumi Miyoshi (QuEL, Inc.) Overview: We aim to improve the performance and reduce the size of the existing frontend by utilizing digital signal processing and packaging the system into a chip/package. In addition, to realize a scalable qubit control frontend, we will implement a high-precision clock distribution system, a high bandwidth and low latency communication mechanism to send/receive data between this frontend and error correction backend, and a control and measurement system with them.
Development Goal: The current signal quality stabilization, which relies on temperature control, will be improved using digital signal processing to compensate for the temperature. The ADCs/DACs, local oscillators, and mixers that make up a unit will be integrated into one or more chips/packages (modules) to reduce their size. As a result, the number of temperature control modules for thermostabilization, such as Peltier elements, will be reduced, and the size and power consumption will be reduced to about 1/3. In addition, a high-precision clock distribution system using optical modules and a control and measurement system synchronized by the clock to collect error syndrome information of 100 physical qubits or more will be developed. The collected syndrome information will be transmitted over a high bandwidth and low latency network using the appropriate data format for the backend system researched and developed by R&D item 1. By combining the above, we will realize a control and measurement system of 100 physical qubits in 1/3 the size of the existing system.

Research and development theme 1: Exploring photonic integrated circuits operating in the extremely low-temperature environment
		Principal Investigator: Jun Shiomi (Osaka University) Overview: This project develops photonic integrated circuits operating in the extremely low-temperature environment. Based on the measurements results of optical elements, we predict the performance of classical-quantum interfaces. We then design and measure optical fundamental module circuits of classical-quantum interfaces. We explore the applicability of optical circuits to scalable error correction systems for quantum computing.
Development Goal: Confirm the operability of opticalintegrated circuits in the low-temperature region by actualmeasurements, and clarify theiroperability. We predict theoperation performance of theclassical-quantum interface fromthe performance of the devicealone. A partial circuit of theclassical-quantum interface circuitis prototyped and its operationperformance is clarified. From theperformance evaluation results ofthe partial circuit, we will clarify theapplicability to a scalable quantumerror correction system, which isthe goal of this project.

Research and development theme 2: Cryo-CMOS PDK Development
		Principal Investigator: Michihiro Shintani (Kyoto Institute of Technology) Development Goal: This project develops a PDK environment that enables the design of large-scale integrated circuits that can withstand the severe power requirements of a 4K environment. For this purpose, we clarify the physical behavior of Si CMOS circuits at cryogenic environment temperature and incorporate it into transistor models. More specifically, we model transistors based on measurements in cryogenic environments and evaluate them using commercial SPICE simulators. We also clarify the characteristic variation and establish the basis for a design environment of scalable error correction systems for quantum computing.

Research and development theme 3: Cryo-CMOS Design Platform
		Principal Investigator: Takashi Sato (Kyoto University) Development Goal: The realization of large-scale Cryo-CMOS integrated circuits at cryogenic temperatures requires a significant reduction in power consumption while guaranteeing the performance of the circuits. This project aims to develop a circuit design methodology with the lowest possible power consumption at cryogenic temperatures. Specifically, we will 1) measure the characteristics of synchronous circuits in cryogenic temperature, 2) develop supply voltage control techniques to reduce dynamic power consumption, which is likely to be an issue at cryogenic temperatures, and 3) develop a foundation for implementing quantum error-correcting classical circuits at cryogenic temperatures.

Research and development theme 1: Digital circuit implementation and reliability enhancement techniques
	Principal Investigator: Kazutoshi Kobayashi (Kyoto Institute of Technology) Development Goal: Accelerate quantum processing that is currently executed in quad-parallel n the FPGA, reduce the amount of hardware, and the power consumption. Further miniaturization and power saving will be achieved by integrating on a chip with RF/ADC/DAC. Then the volume of the quantum control frontend (FE) can be reduced.


Research and development theme 2: RF Frontend Circuit Technology for Scalability
	Principal Investigator: Akira Tsuchiya (The University of Shiga Prefecture) Overview: Integration of RF frontend circuits into ASIC is a promising way to achieve scalability. However, implementation on ASIC rises some problems. The ASIC needs high stability against voltage and temperature fluctuation, and strict suppression of interference among circuits. We develop optimal architecture and design techniques to tackle these problems.
Development Goal: Realization of scalability by RF frontend integration on ASIC.

Research and development theme 3: High-speed DAC for frontend
	Principal Investigator: Nobukazu Takai (Kyoto Institute of Technology) Overview: We develop low-power/high-speed/small-area DAC. We achieve an automatic design of element circuits consist of DAC by using machine learning and a reduction of design time. At the same time, we aim to realize automatic synthesis of circuits, that has never existed before. We prototype and evaluate the automatic designed/synthesized circuits.
Development Goal: Development of architecture for low-power/high-speed/small-area DAC Realization of the algorithm of the automatic design/synthesis of the element circuit of DAC.

Research and development theme 4: High speed ADC for frontend
	Principal Investigator: Masaya Miyahara (High Energy Accelerator Research Organization) Overview: An interleaved ADC with a scalable sampling rate according to system requirements will be realized. For this purpose, high-speed, low-power and compact ADC architecture which suitable interleaved operation will be developed. A calibration method for channel-to-channel mismatches in interleaved ADC which causes performance degradation will also be considered.
Development Goal: Development of high-speed, compact, low-power ADC architecture. Development of calibration method for channel-to-channel mismatch of an interleaved ADC.

Research and development theme 5: RTL design of digital circuits for frontend
	Principal Investigator: Takashi Imagawa (Meiji University) Overview: Based on the front-end digital circuits designed for FPGAs, we design register transfer level (RTL) circuits that can be synthesized for ASICs. The circuit architecture is optimized to enable operation at cryogenic temperatures, that is., low power and small area.
Development Goal: Design space exploration of optimal circuit architecture for low power and small area to enable operation at cryogenic temperatures.

Research and development theme 6: Layout design of digital curcuits for frontend
	Principal Investigator: Ryo Kishida (Toyama Prefectural University) Overview: We design the layout for the frontend digital circuit into the ASIC. The design methodologies will be established for ASIC implementation.
Development Goal: Design of the layout for low power and small size and establishment of consistent design methodologies from logic synthesis to the layout.

Research and development theme 1: Frontend Analog RF LSI at Room Temperature
	Principal Investigator: Masatoshi Igarashi (Socionext Inc.) Overview: To reduce the size of the frontend analog RF part in the qubit controller operating at room temperature, key functional blocks are being developed using advanced CMOS process technologies. The design guideline for CMOS integration will be proposed based on the evaluation results of TEG and identified issues.
Development Goal: This project focuses on the development of the PLL, transmitter, and receiver, which are essential functional blocks in the frontend analog RF part. These blocks will be developed using advanced CMOS process technologies to ensure proper operation at room temperature. To achieve low power consumption and reduced noise, the PLL will be developed with high-speed digital circuits, and the Q factor of devices used in the transmitter and receiver will be improved. Additionally, electromagnetic field analysis will be conducted to study the isolation between the transmitter and receiver integrated on the same die. Furthermore, the integrated TEG, which includes the key functional blocks, will be developed and evaluated. The evaluation results and identified issues will contribute to the proposal of a design guideline for CMOS integration.