| 1. |
杉谷 昇太朗、小林 和淑ほか、”22nmFDSOIプロセスで試作したスタック型フリップフロップのソフトエラー耐性の実測評価”、LSIとシステムのワークショップ2023
https://pdf.gakkai-web.net/ieice/icd/doc/LSI-WS_Poster_Program_rev3.pdf |
| 2. |
中島 隆一、小林 和淑ほか、”PMOSおよびNMOSトランジスタを独立させたソフトエラー感度の測定手法”、LSIとシステムのワークショップ2023
https://pdf.gakkai-web.net/ieice/icd/doc/LSI-WS_Poster_Program_rev3.pdf |
| 3. |
中島 隆一、小林 和淑ほか、”22nm/65nmのFD-SOIプロセスで試作したガードゲートフリップフロップのソフトエラー耐性の実測評価”、LSIとシステムのワークショップ2023
https://pdf.gakkai-web.net/ieice/icd/doc/LSI-WS_Poster_Program_rev3.pdf |
| 4. |
三好 健文： Takefumi Miyoshi et al., "A Fully Pipelined Architecture of Quantum-Classical
Interface for Realizing FaultTolerant Quantum Compute", IEEE International
Conference on Quantum Computing and Engineering (QCE) 2023
DOI: 10.1109/QCE57702.2023.10263
|
| 5. |
大平 龍太郎：”RFSoCを活用した冷却イオン量子ビットのコヒーレント制御”、1st International Workshop on Information Engineering(QIE2023)
https://ken.ieice.org/ken/download/202311168CYB/ |
| 6. |
大平 龍太郎："QuEL-1:A Scalable Quantum Control System for Superconducting Qubits",
Quantum Innovation 2023 |
| 7. |
大塩 達也："Development of an ion-shuttling system for the QCCD architecture",
Quantum Innovation 2023 |
| 8. |
青山 連：”誤り耐性量子コンピュータに向けた22nmバルクプロセスによる上面符号用エラー訂正復号器の設計”、電子情報通信学会 VLSI設計技術研究会（VLD）, 2023
https://ken.ieice.org/ken/paper/202311151CYT/ |
| 9. |
小山 雄輝：”量子コンピュータ制御装置のASIC化に向けた10GbpsクラスDeserializerの開発”、 情報処理学会、第203回システムとLSIの設計技術研究発表会, 2023
SLDM WIP Forum 2023 |
| 10. |
長名 保範：”高性能FPGAクラスタへ向けたEnhernetレイヤの性能測定”、第248回システム・アーキテクチャ・第205回システムとLSIの設計技術・第65回組み込みシステム合同発表会, 2023 |
| 11. |
松尾 亮祐：”超伝導量子ビットのための低コスト制御回路アーキテクチャ”、LSIとシステムのワークショップ2024 |
| 12. |
松尾 亮祐： Ryosuke Matsuo et al., "Succinct pulse generator architecture maximizing
gate fidelity for superconducting quantum computers", 61th Design
Automation Conference 2024
https://arxiv.org/html/2312.08699v2 |
| 13. |
隅田 土詞： Toshi Sumida et al., "QuEL-1: a qubit-controller with broadband electronics",
Swiss-Japanese Quantum Symposium 2024
https://meetings.aps.org/Meeting/MAR24/Session/D49.4 |
| 14. |
三好 健文：”拡張可能なマイクロ波制御イオントラップ量子コンピュータ制御装置の構成方式の検討”、 第50回量子情報技術研究会（QIT50）, 2024
https://ken.ieice.org/ken/paper/20240528uc38/ |
| 15. |
今川 隆司、Takashi Imagawa et al., "A Power Reduction Scheme by Arithmetic Format
Conversion for a DSP to Estimate Qubit States Under 4K Cryogenic Environment",
IEEE International Conference on Quantum Computing and Engineering–QCE24.
https://qce.quantum.ieee.org/2024/wp-content/uploads/sites/8/2024/09/QCE24-Final-Poster-Presentation-Schedule.pdf |
| 16. |
三好 健文、Takefumi Miyoshi et al., "A Microwave-based QCCD Trapped-Ion Quantum Computer with Scalable Control System", IEEE International Conference on Quantum Computing and Engineering–QCE24.
https://qce.quantum.ieee.org/2024/wp-content/uploads/sites/8/2024/09/QCE24-Final-Poster-Presentation-Schedule.pdf |
| 17. |
松尾 亮祐、Ryosuke Matsuo et al., "Cost-effective pulse generator architecture
maximizing gate fidelity for superconducting quantum computers", IEEE
International Conference on Quantum Computing and Engineering–QCE24.
https://qce.quantum.ieee.org/2024/wp-content/uploads/sites/8/2024/09/QCE24-Final-Poster-Presentation-Schedule.pdf |
| 18. |
佐野 健太郎、Jan Erik Reinhard Wichmann et al., "Connecting Physical Qubits to
Quantum Error Correction Backends using Regular Etherneｔ", IEEE International
Conference on Quantum Computing and Engineering–QCE24.
https://qce.quantum.ieee.org/2024/wp-content/uploads/sites/8/2024/09/QCE24-Final-Poster-Presentation-Schedule.pdf |
| 19. |
佐藤 高史、Ruotai Wang et al., "Exploring Surface Code Decoding via Cryo-CMOS for Fault-Tolerant Quantum Computers", IEEE International Conference on Quantum Computing and Engineering–QCE24.
https://qce.quantum.ieee.org/2024/wp-content/uploads/sites/8/2024/09/QCE24-Final-Poster-Presentation-Schedule.pdf |
| 20. |
小山 雄輝： ”量子コンピュータ正業チップ検証用受信回路”、第14回d.lab-VDECデザインアワード
http://www.vdec.u-tokyo.ac.jp/DesignersForum/Forum24.html |
| 21. |
岩瀬 朝生：”極低温環境に最適なGain Cell DRAM”、第14回d.lab-VDECデザインアワード
http://www.vdec.u-tokyo.ac.jp/DesignersForum/Forum24.html |
| 22. |
比嘉 義斗、Y. Higa et al., "A Lossless-Ethernet-based interconnect for FPGA clusters toward FTQC",
IEEE CLUSTER 2024
https://clustercomp.org/2024/program/ |
| 23. |
Jan Erik Reinhard Wichmann et al., "Scalable Connection of Qubits
to Quantum Error Correction Systems using Ethernet", IEEE CLUSTER 2024"
https://clustercomp.org/2024/program/ |
| 24. |
Ryutaro Ohira et al., "Towards a control system for quantum computers
across diverse physical platforms", QUANTUM INNOVATION 2024.
https://quantum-innovation2024.jp/program/files/Proceedings_QI2024.pdf |
| 25. |
岩瀬 朝生：”極低温環境に最適なGain Cell DRAM”、情報処理学会 システムとLSIの設計技術（SLDM）研究会
https://www.ipsj.or.jp/kenkyukai/event/sldm206.html |
| 26. |
岩崎 哲朗：”スパースガウス過程回帰に基づく極低温CMOSコンパクトモデリング”、情報処理学会 システムとLSIの設計技術（SLDM）研究会
https://www.ipsj.or.jp/kenkyukai/event/sldm206.html |
| 27. |
門本 淳一郎、Junichiro Kadomoto et al., ”Preliminary Design Space Exploration for ASIC
Implementation of Control Systems in Fault-Tolerant Quantum Computers”,
IEEE International Conference on Quantum Computing and Engineering–QCE24
https://qce.quantum.ieee.org/2024/wp-content/uploads/sites/8/2024/08/QCE24-Poster-Presentation-Schedule-v67.pdf |
| 28. |
岩瀬 朝生、Tomoki Iwase, Shigeru Yamamoto and Kazutoshi Kobayashi, ”22-nm Gain Cell
DRAM for Cryogenic Operation”, COOL Chips 28 (IEEE Symposium on Low-Power
and High-Speed Chips and Systems)
https://www.coolchips.org/2025/wp-content/uploads/2025/04/05_Program-1-1.pdf
|
| 29. |
土谷 亮：”極低温における配線抵抗率のサイズ依存性が回路設計に与える影響”、LSIとシステムのワークショップ2025
https://pdf.gakkai-web.net/ieice/icd/doc/poster_program_2025v3.pdf
|
| 30. |
Zhipeng Liang：”バルクCMOSトランジスタにおける極低温のForward Body Biasingを用いた電流特性の測定とモデリング”、LSIとシステムのワークショップ2025
https://pdf.gakkai-web.net/ieice/icd/doc/poster_program_2025v3.pdf |
| 31. |
Nilton F. G. FILHO et al., "Error Detection in Fixed-Frequency Transmon Qubits with Distance-9 Repetition Coder"、第52回量子情報技術研究会（QIT52） |
| 32. |
Yoshinori Kurimoto et al., "Long-Term Measurement of Amplitude Stability
in Multi-Channel Microwave Outputs of an In-House Qubit Controller"、第52回量子情報技術研究会（QIT52） |
| 33. |
Ryotaro Ohira, "Development of a Time-Division Multiplexed Electrode
Control System for Trapped-Ion QCCD Architectures",
Quantum Innovation 2025, Program Book. |
| 34. |
Kazutoshi Kobayashi, "Development of Scalable Highly Integrated Quantum
Bit Error Correction System (QUBECS)", Quantum Innovation 2025, Program Book. |
| 35. |
Yoshinori Kurimoto, "Long-Term Stability Assessment of Multi-Channel Microwave Outputs and Theoretical Analysis of the Impact of Static Errors on Quantum Gate Fidelity",
Quantum Innovation 2025, Program Book. |
| 36. |
Tomoki Iwase, "22nm-Gain Cell DRAM for Cryogenic Operation",
Quantum Innovation 2025, Program Book. |
| 37. |
Junsei Tabata, "A Scalable Interconnect for FPGA-Based Quantum Error
Correction Systems toward FTQC",
Quantum Innovation 2025, Program Book. |
| 38. |
Xinyi GUO, "Weighted Range-Constrained Ising-Model Decoder for Quantum
Error Correction",
Quantum Innovation 2025, Program Book. |
| 39. |
Jan-Erik R. Wichmann, "Investigation of Error Statistics in Surface
Codes to Guide QEC Decoder Research",
Quantum Innovation 2025, Program Book. |
| 40. |
Prasoon Ambalathankandy, "Low-Latency FPGA-Based Syndrome Graph Pruning
for scalable Quantum Error Correction Decoders",
Quantum Innovation 2025, Program Book. |
| 41. |
松尾 亮祐：Ryosuke Matsuo, Hidehisa Shiomi and Jun Shiomi, "On-chip optical pulse modulation for scalable superconducting quantum computers", IEEE International Conference on Quantum Computing and Engineering–QCE25
QCE25 Poster Presentation |
| 42. |
Junichiro Kadomoto et al., "Quantifying the Gap Between FPGA and ASIC Implementations of a Surface Code Decoder", IEEE International Conference on Quantum Computing and Engineering–QCE25 |
| 43. |
Ryosuke Matsuo et al., "Towards a Measurement-Based Quantum
Computing Architecture Using Continuous-Variable Optical Qubits",
IEEE International Conference on Quantum Computing and Engineering–QCE25 |
| 44. |
土谷 亮：Akira Tsuchiya, "Mean-Free-Path-Based Modeling of Interconnect
Resistivity for Cryogenic CMOS", International Conference on Solid
State Devices and Materials 2025 (SSDM 2025), PS-01-03 |
| 45. |
Zhipeng Liang et al., "Cryogenic Characterization and Modeling
of Forward Body Biased Current in 180nm Bulk CMOS Transistors", IEEE
International System-on-Chip Conference (SOCC) 2025, PS1A: Poster Session: Late Breaking News |
